1. Field of the Invention
The present invention relates to Electrically Erasable, Electrically Programmable Read Only Memories (EEPROMs), and more particularly but not by way of limitation, to an EEPROM with precisely shaped and placed memory cell elements.
2. Discussion
An Electrically-Erasable, Electrically Programmable Read Only Memory (EEPROM) is a semiconductor device that generally uses field effect transistor memory cells with floating gate structures to store data in a memory array. A fundamental measure of an EEPROM's cost is its chip size. The smaller the chip size, the more chips can be fit onto a fixed-cost silicon wafer. Because the memory array is a large part of the total chip, shrinking the size of each memory cell transistor is one way to minimize chip size. Thus, advances in the art that improve the shape or placement of an element of a memory cell are of great commercial significance.
In current EEPROMs, including Flash EEPROMs herein, memory cells are isolated by the placement of SiO.sub.2, or "field oxide," in the area surrounding a memory cell. The field oxide in typical CMOS memory technologies is formed by a process known as local oxidation of silicon (LOCOS). LOCOS is well known to have certain problems that affect the shape and placement of the field oxide. These problems include (i) the bird's head effect (recessed LOCOS); (ii) the bird's beak effect; and (iii) the white ribbon effect, commonly called the Kooi effect.
The first two of these problems are closely related. In the LOCOS process, a mask is formed and oxide is grown in the exposed regions. At the edges of the mask, however, some oxidant diffuses laterally, resulting in a slowly tapering oxide wedge. The deformation causes a corresponding imprecision in the placement of the field oxide regions with respect to the other elements of the memory cells. Elements of the memory array which could theoretically be perfectly aligned with the edge of the field oxide regions must be offset to allow for the uncertainty in the thickness of the field oxide at the edges. This resulting misalignment limits the minimum distance between memory cells.
Certain other problems inherent in the LOCOS process serve to further increase the distance between memory cells. For example, in processes that use LOCOS to form the field oxide regions of the memory array, various mask steps are required in forming additional elements of the array. Each mask step has a degree of uncertainty associated with the placement of the mask, resulting in a corresponding uncertainty in the placement of the memory element associated with that step of the process. Subsequent mask steps that must align with the memory element not only must compensate for the uncertainty in the placement of the mask, but must also compensate for the uncertainty in the location of the memory element.
In addition, although the field oxide is typically designed to have rectangular sides, photolithographic effects cause the corners of the field oxide to be somewhat rounded, resulting in a field oxide with an oblong shape. The combination of the above effects can cause non-identical adjacent cells, resulting in a broad array erase distribution. Thus, LOCOS field oxide formation results in limitations on desired field oxide shape and placement, necessitating a decreased cell density on the chip.
In addition to the degradation of the shape and placement of the field oxide, the above problems with the LOCOS process also degrade the performance of memory cells in the array. Because the deformation of the field oxide occurs at the edges, the deformation is not generally detrimental to memory cell performance where the memory cell geometries are relatively large. In modern devices with relatively small geometries, however, the detrimental effects of LOCOS field oxide deformation on memory cell performance can be significant.
The capacitive coupling between control gates and floating gates in the memory cell array is improved by extending the floating gate onto field oxide regions adjacent each cell. In particular, degradation of the shape of the field oxide regions impacts the capacitive coupling ratio K.sub.1 between the memory cell control gate and floating gate and the capacitive coupling ratio K.sub.2 between the control gate and the drain. These important design parameters are defined by: EQU K.sub.1 =C.sub.1 /C.sub.T
and EQU K.sub.2 =C.sub.3 /C.sub.T
where EQU C.sub.T =C.sub.2 +C.sub.3 +C.sub.4 +C.sub.5
and
C.sub.1 =capacitance between control gate and the floating gate. PA1 C.sub.2 =capacitance between floating gate and the source. PA1 C.sub.3 =capacitance between floating gate and the drain. PA1 C.sub.4 =capacitance between floating gate and the channel. PA1 C.sub.5 =capacitance between floating gate and the substrate. PA1 V.sub.f =voltage coupled to the floating gate. PA1 V.sub.g =voltage applied at the control gate.
These capacitances are shown schematically in FIG. 1. C.sub.5 the capacitance between floating gate and the substrate through the field oxide can be of importance because of the large coupling area between the floating gate and the control gate located over the field oxide. Thus, variations from the assumed values in C.sub.5 can cause significant change in the key design parameters K.sub.1 and K.sub.2.
Improving the capacitive coupling ratio K.sub.1 between the control gate and the floating gate allows program and erase operations at reduced control gate voltages, and allows improved reading currents during read operations. As K.sub.1 is improved, a greater percentage of the voltage applied to the control gate can be coupled to the floating gate. This relationship is represented by the equation: EQU V.sub.f =K.sub.1 V.sub.g
where
If the field oxide is oblong, however, K.sub.1 decreases, requiring a greater voltage to be applied to the control gale to achieve the same potential on the floating gate. In addition, oblong Field oxide contributes to a wide erase distribution in a memory array.
Accordingly, there is a need for an EEPROM and a process for making same that has increased precision in the shape and placement of the field oxide regions, improves the capacitive coupling ratio for the memory cells, and tightens the intrinsic erase distribution of a memory array.